The present invention relates to a frequency control and phase lock circuit. More particularly, it relates to a frequency control and phase lock circuit which is capable of high-speed and stable phase synchronization pull-in reproduction of a clock for reproducing a digital signal which is recorded on an optical disk medium, utilizing a linear velocity cycle detected from a reproduced signal, also in a situation where the linear velocity cycle of the reproduced signal varies.
As a method of recording digital data on an optical disk medium, a method in which the recording is performed at a constant linear velocity to equalize the recording density on the recording medium is used in many cases as can be seen in the case of CDs (Compact Disks) or DVDs. In a case where the phase synchronization pull-in is performed for an optical disk reproduced signal which was subjected to the mark-length modulation and digital modulation to obtain a constant linear recording density, when the difference between the frequency of the clock component of the reproduced signal and the frequency of the clock generated by a phase-locked loop circuit is large, there is a great risk of uncompleted phase synchronization pull-in or pseudo pull-in to a frequency which is different from that of the clock component of the reproduced signal. In order to avoid these situations, the reproduction linear velocity cycle is detected on the basis of the pulse length or pulse interval of a specific pulse included in the reproduced signal, and control of the rotational speed of the disc or control of the free-running frequency of the phase-locked loop is performed, whereby the normal phase synchronization pull-in can be realized.
For example, there is a disc reproduction system as shown in FIG. 12. Data as shown in FIG. 14(a) are recorded on an optical disk 47 so as to have a constant linear recording density. Assume that the recorded data are controlled to have 3 or more and 14 or less consecutive xe2x80x9c0xe2x80x9ds or xe2x80x9c1xe2x80x9ds, as in the 8-16 modulation system. The amplitude of a signal which is reproduced by a reproduction means 48 is attenuates in higher-band frequency components due to the interference, as the linear recording density of the recorded data increases. Thus, this signal is subjected to the compensation by a waveform equalization means 1 to emphasize the higher-band frequency components. The emphasized reproduced signal (FIG. 14(b)) is binarized at a predetermined slice level by a binarization means 49, to be converted into a binarized digital signal (FIG. 14(c)).
Then, a cycle detection means 50 counts the cycle of a specific pattern of the digital signal which was binarized by the binarization means 49, using a high-frequency clock. The high frequency clock which is used here is generated by an oscillator 51. In this case, the oscillator 51 is a crystal oscillator which stably oscillates at a fixed frequency, or the like. As shown in FIG. 13, the cycle detection means 50 consists of a counter means 52 continuously counting a pulse width or pulse interval of a specific pulse which is counted using the high-frequency clock, a holding means 53 holding a count result which is just previously obtained by the counter means 52, an addition means 54 receiving a result which is output by the counter means 52 and the data which are held and output by the holding means 53, and adding the two consecutive counted pulse width or pulse interval results, and a judgement means 55 obtaining the maximum value or minimum value of the outputs of the addition means 54 at every predetermined period. The cycle detection means 50 obtains the maximum value or minimum value of the sum of the two consecutive pulse widths (or pulse intervals). The information obtained by the cycle detection means 50 is inversely proportional to the linear velocity and includes cycle information of the clock of the reproduced signal. Therefore, the control is performed on the basis of this information so that the free-running frequency of the phase-locked loop circuit 56 nearly matches the frequency of the clock component of the reproduced signal. In this case, a phase-locked loop circuit 56 consists of a phase comparator 57, a charge pump 58, a loop filter 59 and a VCO. 60. This VCO 60 adaptively operates the center frequency on the basis of the frequency information obtained by the cycle detection means 50, and performs the control so that the oscillated frequency almost matches the frequency of the clock component of the digital signal which is obtained by the binarization means 49. Thereby, the phase synchronization pull-in can be completed without waiting until the rotation of a motor is settled near the stationary rotation at a timing of starting the reproduction of the disc or immediately after the seek at the CLV reproduction time when the reproduction is performed at a constant linear velocity.
For example in the CAV reproduction in which data are reproduced with fixing the rotation speed of the motor for rotating the recording medium, the linear velocity of the reproduced data varies according to whether an accessed area is on an inner track or outer track of the disc. Assume that the frequency which is synchronized with that of the reproduced data is 20 MHz at an inner track position A and 40 MHz at an outer track position B as shown in FIG. 15, and the high-frequency clock which is output by the oscillator 51 is at 100 MHz. In this case, when a DVD is reproduced, the reproduced signal has a synchronization pattern consisting of contiguous 14T and 4T as shown in FIG. 16(a) at regular periods. Here, T is a period corresponding to 1 bit of a recording code included in the reproduced signal. When the pattern length of this synchronization pattern is counted using a 100-MHz high frequency clock, a detected count value is (14+4)xc3x97100/20=90 at the inner track position A as shown in FIG. 16(b) and (14+4) xc3x97100/40=45 at the outer track position B as shown in FIG. 16(c). Therefore, it is understood that the count value obtained using the high-frequency clock is information which is inversely proportional to the linear velocity at the reproduction position. Utilizing this principle, assuming that the data at the outer track position B are sought in a state where the data at the inner track position A are being reproduced, the reproduction clock which is output by the VCO 60 is at 20 MHz just after the seeking, which is the phase-locked frequency at the inner track position A, as shown in FIG. 17. However, when the synchronization pattern is counted using the 100-MHz high-frequency clock and the obtained count number is 45, the feedback is performed so that the reproduction clock output by the VCO 60 approaches 40 MHz according to estimates from the cycle information. The processing is performed up to the area where the phase synchronization pull-in can be performed. Then, the phases of the reproduced data and reproduction clock can be synchronized by the phase-locked loop circuit 56.
However, when the high-frequency clock is used in the above-described means for detecting the cycle from the reproduced signal, the oscillator for generating the high-frequency clock is required. In addition, when the reproduction is to be performed at higher speed with an increased rotation of the motor, it is required to calculate the cycle according to the reproduction speed. On the other hand, in order to simplify the cycle calculation, it is required to change the oscillated frequency of the high-frequency clock in proportion to the rotational speed of the motor. Further, in order to improve the precision of the cycle detection means, it is desirable to utilize the pattern length and pattern interval of synchronization patterns which are included in the recorded data at regular intervals. However, in the case where the detection of the pattern length and pattern interval of the synchronization patterns is used for detecting the cycle from the reproduced signal, when the deviation between the frequency of the clock component of the reproduced signal and the frequency of the clock generated by the phase-locked loop circuit is large, the precision in detection of the synchronization patterns in detecting the frequency deviation or the like should be regarded as important. Accordingly, the time for specifying the synchronization pattern is increased, whereby the efficiency in detection of the synchronization pattern, which is required in high-speed frequency pull-in, is decreased. Further, the phase of the high-frequency clock used in the cycle detection means is not synchronized with the phase of the frequency of the clock component of the reproduced data, and thereby the detection results vary. Thus, particularly when the linear velocity of the reproduced data continuously varies during the reproduction period after phase locking, the detection precision is deteriorated.
The present invention is made to solve these problems of the prior art. It is an object of the present invention to provide a frequency control and phase lock circuit, by constructing the means for detecting the linear velocity cycle information from a reproduced signal so as to detect cycle information and phase information from multi-bit reproduced digital data which are obtained by the sampling using a reproduction clock which is used instead of the high-frequency clock, performing the control so as to synchronize the phase of the reproduction clock with the phase of the clock component of the reproduced digital data on the basis of this information, and thereby unifying the clock into one system, whereby the high-speed and stable phase synchronization pull-in can be realized using the reproduction clock also in a state where the linear velocity of reproduced digital data varies.
A frequency control and phase lock circuit according to the present invention comprises: waveform equalization means for emphasizing a predetermined frequency band of a reproduced signal; an A/D converter for sampling a signal equalized by the waveform equalization means to obtain multi-bit digital data using a reproduction clock to be used when the equalized signal is reproduced as digital data; low-band noise suppression means for suppressing low-band noises in the signal obtained by the sampling on the basis of the reproduction clock; a zero cross length detector for detecting a position where the signal crosses a zero level, the low-band noises of which signal are suppressed, counting a number of samples between adjacent zero crosses on the basis of the reproduction clock, and holding the number of samples in a register; a frame counter for counting a specific period of at least one frame; a maximum pattern length detector and a minimum pattern length detector for detecting a maximum value and a minimum value of count values of zero cross lengths in the specific period counted by the frame counter or sums of count values of adjacent zero cross lengths, respectively; a cycle information judgement unit for comparing the maximum pattern length with the minimum pattern length, and selecting an optimal value as cycle information using a ratio between the maximum and minimum pattern lengths; a frequency error detector having both of means for converting a difference between the cycle information which is selected by the cycle information judgement unit and the maximum or minimum pattern length which is to be detected at a phase-locked time, into a frequency error and outputting the frequency error, and means for judging a synchronization pattern from the maximum pattern length, converting an interval between the synchronization patterns into a frequency error and outputting the frequency error; a frequency control circuit for performing control as far as an area where the reproduction clock can be synchronized with the reproduced digital signal on the basis of an output of the frequency error detector; a phase error detector for detecting phase information from the signal, the low-band noises of which signal are suppressed; a phase control circuit for performing phase control so that reproduction clock is in phase with the reproduced digital signal on the basis of an output of the phase error detector; and an oscillator for adding an output of the frequency control circuit and an output of the phase control circuit, and oscillating a reproduction clock on the basis of the sum, thereby enabling phase synchronization pull-in at a time of reproduction of the digital data, whereby the above-mentioned problems are solved.
According to the present invention, the reproduction clock is used in place of the high-frequency clock, the cycle information and the phase information is detected from multi-bit reproduced digital data which are obtained by the sampling on the basis of the reproduction clock, and the control is performed so as to synchronize the phase of the reproduction clock with the phase of the clock component of the reproduced digital data, whereby the clock can be unified into one system. Therefore, the high-speed and stable phase synchronization pull-in can be realized using the reproduction clock, also in a state where the linear velocity of the reproduced digital data varies.
A frequency control and phase lock circuit according to on embodiment of the present invention comprises: waveform equalization means for emphasizing a predetermined frequency band of a reproduced signal; an A/D converter for sampling an equalized signal to obtain multi-bit digital data using a reproduction clock to be used when the equalized signal is reproduced as digital data; low-band noise suppression means for suppressing low-band noises in the signal obtained by the sampling; a zero cross length detector for detecting a position where the signal crosses a zero level, the low-band noises of which signal are suppressed, counting a number of samples between adjacent zero crosses, and holding the number of samples in a register; a frame counter for counting a specific period of at least one frame; a maximum pattern length detector and a minimum pattern length detector for detecting a maximum value and a minimum value of count values of zero cross lengths in the counted specific period or sums of count values of adjacent zero cross lengths, respectively; a cycle information judgement unit for comparing the maximum pattern length with the minimum pattern length, and selecting an optimal value of the pattern length as cycle information using a ratio between the maximum and minimum pattern lengths; a frequency error detector for converting a difference between the cycle information which is selected by the cycle information judgement unit and the maximum or minimum pattern length which is to be detected at a phase-locked time, into a frequency error, and outputting the frequency error; a frequency control circuit for performing control as far as an area where the reproduction clock can be synchronized with the reproduced digital signal on the basis of an output of the frequency error detector; a phase error detector for detecting phase information from the signal, the low-band noises of which signal are suppressed; a phase control circuit for performing phase control so that reproduction clock is in phase with the reproduced digital signal on the basis of an output of the phase error detector; and an oscillator for adding an output of the frequency control circuit and an output of the phase control circuit, and oscillating a reproduction clock on the basis of the sum, and the frequency control and phase lock circuit enables phase synchronization pull-in at a time of reproduction of the digital data.
Therefore, the high-frequency clock for detecting the cycle and the oscillator for the high-frequency clock can be dispensed with. Accordingly, not only the circuit construction can be simplified, but also the stable phase synchronization pull-in can be realized also in a state where the linear velocity of the reproduced digital data varies, because the reproduced digital data and the frequency error information can be generated using one clock. In addition, an optimal one of the maximum pattern length and the minimum pattern length is selected and utilized as the frequency error. Therefore, not only the frequency pull-in of the reproduction clock can be performed at high speed, but also the frequency control can be performed also at the seeking time when the cycle detection is regarded as difficult.
According to another embodiment of the present invention, in the frequency control and phase lock circuit of the above-discussed embodiment, the maximum pattern length detector has a synchronization pattern judgement unit for judging whether a pattern is a synchronization pattern based on a ratio between adjacent zero cross lengths, and updates the maximum pattern length only when the judgement unit judges that the pattern is the synchronization pattern and has a value larger than a held value, and the minimum pattern length detector has a minimum inversion pattern judgement unit for judging whether a pattern is a minimum inversion pattern based on a ration between the adjacent zero cross lengths, and updates the minimum pattern length only when the judgement unit judges that the pattern is the minimum inversion pattern and has a value smaller than a held value.
Therefore, the pattern can be detected with high precision also in the case where the deviation between the frequency of the reproduction clock and the frequency of the clock component of the reproduced digital data is large. Accordingly, the precision in the cycle detection is increased, whereby the frequency pull-in of the reproduction clock can be performed stably.
According to another embodiment of the present invention, in the frequency control and phase lock circuit of an above-discussed embodiment, the cycle information judgement unit comprises: registers for holding the maximum pattern length and the minimum pattern length which are obtained within the specific period counted by the frame counter, at a termination of the period, respectively; and means for automatically setting a period which is to be counted next by the frame counter, based on the pattern length which is obtained as a result of the comparison by the cycle information judgement unit between the values which are held respectively by the registers, the obtained pattern length being regarded as optimal as the cycle information.
Therefore, the detection period for detecting one synchronization pattern included in one frame can be automatically decided based on the frequency information, whereby the efficiency in detecting the synchronization pattern is improved and the frequency pull-in of the reproduction clock can be performed at high speed.
According to another embodiment of the present invention, in the frequency control and phase lock circuit of an above-discussed embodiment, the frequency error detector comprises: synchronization pattern position detection means for detecting a position of a synchronization pattern, using the sum of the adjacent zero cross lengths detected by the zero cross length detector, the judgement result output by the synchronization pattern judgement unit, and the maximum pattern length held by the register; and means for detecting an interval between the synchronization patterns on the basis of a result of the detection, converting the value of the interval into frequency error information, and outputting the frequency error information, and the frequency control and phase lock circuit has a function of switching the precision in detecting the synchronization pattern position by the synchronization pattern position detection means according to deviation between a frequency of the reproduction clock of the synchronization pattern and a frequency of a clock component of the reproduced digital data detected by the frequency error detector.
Therefore, the appropriate synchronization pattern position can be detected according to the amount of deviation between the frequency of the reproduction clock and the frequency of the clock component of the reproduced digital data. Accordingly, not only the precision in detection of the synchronization pattern interval is increased, but also the resolution of the cycle information is increased with respect to the case where the pattern length is detected. Therefore, the cycle can be detected with high precision, whereby the frequency of the reproduction clock can be pulled in stably as far as an area where the reproduction clock can be in phase with the reproduced digital data.
According to anther embodiment of the present invention, in the frequency control and phase lock circuit of an above-discussed embodiment, the frequency error detector has a counter for counting a period during which no synchronization pattern is detected, based on the reproduction clock, and when a count value of the counter is larger than a predetermined value, a mode control circuit for deciding a control state of the frequency control and phase lock circuit sets again plural mode signals output by the mode control circuit in a specific state.
Therefore, the abnormal state is judged by calculating the period during which the synchronization pattern is not detected, and when the state is judged as abnormal, the self-restoration operation is performed. Accordingly, the restoration time at the abnormal operation can be reduced.
According to another embodiment of the present invention, the frequency control and phase lock circuit of an above-discussed embodiment comprises: a frequency error converter for converting the frequency error information output by the frequency error detector, which information is obtained by converting the interval between the synchronization patterns, into phase error information, and outputting the phase error information, and in the frequency control and phase lock circuit, the phase control circuit is operated based on the output phase error information, and the reproduction clock is pulled-in with high precision as far as a frequency area where the phase locking can be performed.
Therefore, the phase control circuit is operated based on the cycle information which is detected by the frequency control circuit, and the frequency of the reproduction clock can be brought closer to the frequency of the clock component of the reproduced digital data by the resolution of the frequency which can be controlled by the frequency control circuit or more. Accordingly, even when the capture range as the phase pull-in range of the phase-locked loop is narrow, the stable phase synchronization pull-in can be realized.
According to another embodiment of the present invention, the frequency control and phase lock circuit of an above-discussed embodiment comprises: both of the functions of the frequency error detector of one of the above-discussed embodiments and the frequency error detector of another of the above-discussed embodiments, and in the frequency control and phase lock circuit, the frequency of the reproduction clock is controlled based on the pattern length of the specific pattern in an area where the deviation between the frequency of the reproduction clock and the frequency of the clock component of the reproduced digital data is larger, and the frequency of the reproduction clock is controlled based on the interval between the synchronization patterns in an area where the deviation is smaller, the deviation in the frequency between the reproduction clock and the clock component of the reproduced digital data is obtained, and the control state is switched continuously and automatically using the plural mode signals which are output by the mode control circuit for deciding the control state of the frequency control and phase lock circuit, thereby pulling-in the frequency of the reproduction clock.
Therefore, in the area where the deviation between the frequency of the reproduction clock and the frequency of the clock component of the reproduced digital signal is larger, the pattern length of the specific pattern can be more easily detected than the synchronization pattern interval. In the area where the deviation in the frequency is smaller, the synchronization pattern interval can be detected with higher precision. Therefore, the frequency pull-in and the phase synchronization pull-in can be performed at high speed and with good stability by the control utilizing the respective advantages.
According to another embodiment of the present invention, the frequency control and phase lock circuit of an above-discussed embodiment comprises: phase control range detection means for detecting that one of the plural mode signals for deciding the control state, which are output by the mode control circuit, indicates that the reproduction clock is in phase with the reproduced digital signal and the phase control circuit operates outside a control range of predetermined values, and outputting a flag, and in the frequency control and phase lock circuit, the operation of the frequency control circuit is controlled so that the operation of the phase control circuit comes within the predetermined range, when the flag output by the phase control range detection means is detected.
Therefore, even when the linear velocity of the reproduced data varies after the phase synchronization pull-in, the phase locked state can be maintained stably.